Optimal design of macrocells for low power and high speed

With the emergence of portable products as major players in the electronics market, controlling the power dissipation of integrated circuits is gaining increased importance. While progress is being made in improved battery technology to supply a larger amount of power per unit weight of the battery, it must also be coupled with an accompanying reduction in the power dissipation of IC's. Even for nonportable applications, as the system complexity increases, it is becoming more and more important to limit the power dissipation so as to avoid additional costs for cooling down electronic systems. In this context, it has become increasingly important to design CMOS digital circuits to ensure a low power dissipation. At the same time, however, it is also necessary to ensure that the speed of the circuit is not unduly sacri ced. An additional consideration is the need for fast system turnaround times, which necessitates the use of semicustom design styles. In this work, we address a design style using exible macrocells [1], where a library of basic functional elements, or macrocells, is constructed. In this work, we present an accurate way of assessing the power dissipation and delay of a macrocell as a function of its transistor sizes, and use an interface with SPICE to ensure that the delay and power calculations are precise. The use of SPICE ensures that power and delay measurements can be made highly accurate using high order models. Moreover, e ects such as the variations in parasitic capacitances with voltage, channel length modulation and the body e ect, to name just a few are measured accurately; these e ects are completely ignored by coarser models. This is very important since a macrocell is designed once and only once. At the end of this procedure, an accurate measure of the worst-case delay and worst-case power dissipation of the macrocell is available.